The present invention is related in general to the field of electronic systems and semiconductor devices and more specifically to improved systems and methods for electrically modeling an electronic structure such as an integrated circuit package and assembly.
Designers of semiconductor integrated circuits (ICs) have used modeling of electrical characteristics for a long time in order to arrive at optimized layouts for the ICs. One of the best known IC modeling systems is called SPICE (xe2x80x9cSimulation Programs for Integrated Circuits in Electronicsxe2x80x9d). For the package, however, which encapsulates the IC no such modeling system exists. Packages are not fine-tuned to leave the IC characteristics undiminished; for example, loss of speed, frequency limitations, cross talk, noise are often observed.
These limitations have become intolerable for the increasing performance demands on ICs. The trends of leadership chips, to be matched by their prospective packages, call for 100 picoseconds edge rates, equivalent to more than 2.6 gigabit/second clocks; lead counts in excess of 1000; collapsing power rails at 1.8 volts, calling for lower noise budget; higher power dissipation, requiring higher capabilities for changing current in time; packages less than 1 millimeter thick; tighter package lead pitch; and last but not least, lower cost.
It is that market trend listed last which is now becoming all-pervasive. As a consequence, the cycle time needed to design a new package is soon required to shrink to approximately 2 weeks; furthermore, it is becoming more and more mandatory to use mostly low cost materials and existing installed manufacturing machines. In addition, reliability expectations for the semiconductor device are increasing in order to lower the cost of ownership; designing-in and building-in reliability through optimized design and process control are the methods proposed to reach the improved product reliability.
In order to meet these often conflicting requirements and to support these ambitious trends, the electrical design of packages for IC devices must more and more be based on sensitive modeling and analysis. Guided by the Semiconductor Research Corporation (SRC), universities such as the University of Arizona at Tucson or the University of California at Berkeley, have been creating and developing electrical simulation and analysis programs for semiconductor packages for several years. While these calculation programs are accurate, their application turned out to be cumbersome in the practical world of industry designers, and sometimes unnecessarily detailed. Unfortunately, there is no system available in known technology which combines a straightforward application of the electrical programs developed at universities with user-friendly features of simplicity, flexibility, and time saving as required by the competitive reality of the semiconductor industry.
An urgent need has therefore arisen for a low-cost, fast and reliable system and a method of operation providing electrical modeling and analysis of electronic structures. The system should provide the opportunity to model the electrical performance of complete semiconductor packages as well as individual parts of it, packages alone as well as in combination with the integrated circuit chip, and semiconductor devices assembled on boards. The system and method should be flexible enough to be applied for different semiconductor product families and a wide spectrum of design, material and process variations, and should spearhead the way for very high frequency, high power packages, as well as toward the goals of improved product yield and device reliability. Preferably, these innovations should be accomplished using conventional workstation and personal computers so that no investment in powerful computing equipment is needed.
According to the electrical modeling system and method provided by the present invention, the electronic structure to be modeled is segmented into an ordered sequence of sections, each section is electrically analyzed individually, and the resulting data is collated, or integrated back again to create the electrical model of the complete structure, whereby the model output is preferably created in a format generally suitable for electrical models of integrated circuits. Examples of electronic structures which can be modeled by the system and method of the invention include leadframes, packages, complete devices, and electronic devices assembled on motherboards.
The present invention is related to high density ICs, especially those to be used at very high frequencies and having high numbers of input/outputs and tight constraints in package outline and profile. These ICs can be found in many semiconductor device families such as processors, standard linear and logic products, digital and analog devices, high frequency and high power devices, and both large and small area chip categories. Since the invention aims at designing devices with minimum geometries and high reliability, it supports continually shrinking applications such as cellular communications, pagers, hard disk drives, laptop computers and medical instrumentation.
It is an object of the present invention to provide an automated system and method for electrically modeling an electronic structure. The object is achieved by an embodiment of the invention using a computer system and a computer-implemented method for automatically analyzing and modeling the electronic structure.
Another object of the present invention is to provide a highly flexible system and method. This object is achieved by the embodiments of four subsystems of the invention:
A user-friendly interface operable to accept user instructions and to control the system operations at a plurality of software control points.
An input data generator operable to accept graphical and geometric inputs, to create patterns of electrical conductors and insulators, and to accept compositional and functional parameters.
A model data analyzer operable to perform two-dimensional and three-dimensional analyses and mixtures thereof.
A model output generator operable to create the model in a plurality of formats, especially those suitable to interface with electrical IC models.
Another object of the present invention is to provide an electrical model of an electronic structure in fast turn-around time and with minimum effort by taking full advantage of symmetries and branching of the structure. This object has been achieved by the embodiments of three-subsystems of the invention:
A segmentation generator operable to select segments of the structure to be modeled and to organize the sequence of these segments.
An analysis generator operable to electrically analyze those segments in a plurality of calculation programs, executed in sequence.
An integrator operable to collate and integrate the analysis results in controlled sequence into a single model.
Another object of the present invention is to introduce modeling concepts which are flexible so that they can be applied to many families of electronic structuresxe2x80x94reaching from piece parts, such as leadframes, to device packages, to complete semiconductor IC products, to electronic substrates, and to whole assemblies on motherboardsxe2x80x94and are general so that they can be applied to several generations of products.
These objects have been achieved by teachings and embodiments of the invention. Various modifications have been successfully employed to satisfy different selections of product geometries, compositions and characteristics. The method of the invention provides easy expansion to new fields of IC modeling, such as inclusion of three-dimensional contributions, or transmission and shielding effects in ultra-high frequency products. Further, the method of the invention provides easy specialization to customer-specific requirements, such as ranking of the options for minimizing certain product parameters.
The technical advances represented by the invention, as well as the objects thereof, will become apparent from the following description of the preferred embodiments of the invention, when considered in conjunction with the accompanying drawings and the novel features set forth in the appended claims.